What is Static Timing Analysis?

Introduction

            Timing analysis is a method of analyzing and solving timing problems to ensure that the design meets the target frequency. Critical timing information such as critical path delays and margins are extracted using the so called, Static Timing Analysis (STA) tool, where each delay elements are pre- characterized and propagated through the timing graph of the given design. Dynamic simulations for timing analysis is no more useful for quick timing closures as multi-core processors are large in size, for reasons like complexity of designs, spice convergence, menial task of probing critical paths etc., here a new technique is approached to handle STA on analog circuits. Pre-layout timing analysis is carried to fix the timing problems before the layout construction, since changing layout takes more time than changing schematics. Post layout is the final timing analysis with extracted parasitics. It is difficult to calculate setup and hold time violations by running STA on large designs like microprocessors. So it is simple by dividing design in to smaller designs called FUBs (Functional Unit Blocks), and collection of FUBs are called Unit. A FUB represents actual physical hardware units of distinct functionality. A well defined and compact interface exists between FUB and neighboring FUB.

Depending on the design methodologies used, two types of timing analysis methods are commonly used: Static timing analysis and dynamic timing analysis.

Static Timing Analysis

It is a non-simulation approach used to analyze propagation of delays. It computes the worst case path delays by accumulating precharacterized device delays along a given path. it does not require any input vectors to analyze the worst case delays. It allows you to run analyses on large circuits fast, but at the expense of accuracy. STA has produced a reasonably accurate timing result in the pre-silicon design phase and helped the designer to properly optimize their design to meet the given timing specification (e.g. operating frequency). 

Dynamic Timing Analysis

It is a Circuit simulation for obtaining a very accurate timing analysis of a path, using input waveforms and generating output waveforms. It is more accurate, but much slower than static timing analysis. Generally used for analog and small specific circuits. It is not path oriented, if dynamic approach results may not match the expected values, then to solve that we have to bedug the path causing the problem. If the design is large it is difficult to analyze the root cause.