Physical Design Interview questions

1. What are the inputs you get for Block level Physical Design?
• Netlist (.v /.vhd)
• Timing Libraries (.lib/.db)
• Library Exchange Format (LEF)
• Technology files (.tf/.tech.lef)
• Constrains (SDC)
• Power Specification File
• Clock Tree Constrains
• Optimization requirements
• IO Ports file
• Floorplan file
2. What are the different checks you do on the Input Netlist.
• Floating Pins
• Unconstrained pins
• Undriven input ports
• Unloaded output ports
• Pin direction mismatches
• Multiple Drivers
• Zero wire load Timing checks
• Issues with respect to the Library file, Timing Constraints, IOs and Optimization requirements.
3. How to do macro Placement in a block
• Analyse the fly-line for connectivity between Macros to Macros and between the Macros to IO ports.
• Group and Place the same hierarchy Macros together.
• Calculate/Estimate the Channel length required between Macros.
• Avoid odd shapes
• Place macros around the block periphery, so that core area will have common logic.
• Keep enough room around Macros for IO routing.
• Give necessary blockages around the Macros like Halo around the macros.
4. What are the issues you see if floorplan is bad.
• Congestion near Macro corners due to insufficient placement blockage.
• Standard cell placement in narrow channels led to congestion.
• Macros of same partition which are placed far apart can cause timing violation.
5. What are different optimization techniques?
• Cell Sizing: Size up or down to meet timing/area.
• Vt Swapping
• Cloning: fanout reduction
• Buffering: Buffers are added in the middle of long net paths to reduce the delay.
• Logical restructuring: Breaking complex cells to simpler cells or vice versa
• Pin swapping
6. What are the inputs for the CTS.
• CTS SDC
• Max Skew
• Max and Min Insertion Delay
• Max Transition, Capacitance, Fanout
• No of Buffer levels
• Buffer/Inverter list
• Clock Tree Routing Metal Layers
• Clock tree Root pin, Leaf Pin, Preserve pin, through pin and exclude pin
7. Why the Metal Fill is required
• If there is lot of gap between the routed metal layers (empty tracks), during the process of Etching the etching material used will fall more in this gap due to which Over Etching of existing metal occurs which may create opens. So in order to have uniform Metal Density across the chip, Dummy Metal is added in these empty tracks.
8. What is Metal Fill
• Metal Density Rule helps to avoid Over Etching or Metal Erosion.
• Fill the empty metal tracks with metal shapes to meet the metal density rules.
• There are two types of Metal Fill
1. Floating Metal Fill: Does not completely shield the aggressor nets, so SI will be there.
2. Grounded Metal Fill: Completely shield the aggressor nets, less SI
9. What are the reasons for routing congestion
• Inefficient floorplan
• Macro placement or macro channels is not proper.
• Placement blockages not given
• No Macro to Macro channel space given.
• High cell density
• High local utilization
• High number of complex cells like AOI/OAI cells which has more pin count are placed together.
• Placement of std cells near macros
• Logic optimization is not properly done.
• Pin density is more on edge of block
• Buffers added too many while optimization
• IO ports are crisscrossed, it needs to be properly aligned in order.
10. What are the different methods to reduce congestion.
• Review the floorplan/macro placements according to the block size and port placement.
• Add proper placement blockages in channels and around the macro boundaries.
• Reduce the local density using the percentage utilization/density screens.
• Cell padding is applied for high pin density cells, like AOI/OAI.
• Check and reorder scan chain if needed.
• Run the congestion driven placement with high effort.
• Check the power network is proper and on routing tract. If it is not on track, adjacent routing tracts may not be used, so it might lead to congestion