Temperature Inversion

In Current equation, I = K.μ.( VGS - VTH)2 ; where mobility (μ) and Threshold Voltage (VTH) are functions of Temperature

At high voltage μ determines the Drain current where as at lower voltages VTH determines the drain current. So at higher voltages device delay increase with temperature but at lower voltages, device delay decreases with temperature

At advanced Technology Nodes though the Threshold Voltage has not reduced much, but the Gate Overdrive Voltage has reduced due to the reduction of supply voltages

Temperature Inversion Effects are more observed in Technology Nodes below 40nm

Multiple Patterning

• Involves decomposing the design across multiple masks to allow the printing of tighter pitches

• 38-nm features with 193-nm light water immersion lithography is the limitation with the current lithographic process

• Multiple Patterning is a technique used in the lithographic process that can create the features less than 38nm at advanced process nodes

• Multiple patterning basically changing the value of K1 in the Critical Dimension equation

Double Patterning

• Double patterning counters the effects of diffraction in optical lithography
• Diffraction effects makes it difficult to produce accurately defined deep sub-micron patterns using existing lighting sources and conventional masks
• Diffraction effects makes sharp corners and edges become blur, and some small features on the mask won’t appear on the wafer at all
• Double patterning is expensive because it uses two masks to define a layer that was defined with one at previous process nodes

Design for Manufacturability (DFM)

• Techniques to ensure the design can manufacture successfully with high yield
• To ensures survival of the design, during the complex fabrication process
• Lithography, etch, Chemical Mechanical Polishing (CMP), and mask systematic manufacturing variations surpass random variations as the prime limiters to catastrophic and parametric yield loss

Need for DFM

• Current Lithographic techniques (193nm Laser) cannot print deep-submicron technology patterns without distortion
• Higher design complexity and shrinking device geometries
• More devices per unit area on a chip (device density)

Importance of DFM

• Impact of variations, if not addressed in the design, will cause manufacturing issues, such as poor yields, long yield ramp-up times and poor reliability
• The chips may completely miss the market window or may hit the market window but not economically viable
• The chips may still function, but not at the required/expected speed
• The chips appear to be reliable after volume production, but may suffer catastrophic failures in the field earlier than their expected life-cycle