Physical Design Inputs

Physical Design Inputs

• Netlist (.v /.vhd)
• It contains Cell name and drive strength.
• Macros
• Standard cells ports
• Interconnection details
• Timing Libraries (.lib/.db)
• Logical view of the cells (std cell lib
• Library Exchange Format (LEF)
• Technology files (.tf/.tech.lef)
• Constrains
• Timing constraints like Clock Definition, Timing Exceptions (False Paths, Asynchronous paths)
• Delay Constraints like Latency, Input Delay, Input Transition, output Load and Output Transition.
• Power and Area constraints
• Design Rule constrains like Max Fanout, Max cap, max Transition
• Clock Uncertainty.
• Operating Conditions
• Power Specification Files
• Power Domains or ON/OFF regions
• PG nets
• Clock Tree Constrains
• Clock Def point.
• Insertion delay
• Skew Target
• Man Cap/Tran/Fanout
• Buffer levels
• List of Buffers/Inverters to use.
• NDR rules for Clock routing.
• Optimization requirements
• Dont use cells 
• Size only or use only cells
• IO Ports file
• Port locations
• Floorplan file