AOCV

• In lower nodes with increasing process, voltage, and temperature variations across the same die, arriving at a single Global derate number is difficult.
• OCV analysis results in reduced design performance, and longer timing closure cycles
• AOCV on the other hand  uses intelligent techniques for specific derating instead of a single global derate value
• AOCV provides a solution for longer timing closure, reduced design performance that caused with OCV analysis.
• In AOCV analysis variable values are used for derating timing paths
• Derate values are functions of Logic depth and/or net and cell location

Using silicon data from test-chips Advanced OCV computes the length of the diagonal of the bounding box. Based on the length calculated appropriate derate value is picked from the AOCV table. 

Floorplanning

Steps in Floorplan

• Initialize with Chip & Core Aspect Ratio (AR)
• Initialize with Core Utilization
• Initialize Row Configuration & Cell Orientation
• Provide the Core to Pad/ IO spacing (Core to IO clearance)
• Pins/ Pads Placement
• Macro Placement by Fly-line Analysis
• Macro Placement requirements are also need to consider
• Blockage Management (Placement/ Routing)

Macro Placement

• Fly-line Analysis (For Connectivity information)
• Macro keep-out (For Uniform Standard Cell Region)
• Channel Calculation (Critical for Congestion and Timing)
• Avoid odd shaped area for Standard Cells
• Funnel shaped Macro Placements are preferred
• Fix the Macro locations, so that tool wont alter during Optimization
• Sufficient Spacing between Macros

Macro Placement Tips

• Place macros around chip periphery, so that core area will be clustered
• Consider connections to fixed cells when placing Macros
• In advanced Technology Nodes Macro Orientation is fixed since the Poly Orientation can’t vary, so there will be restrictions in Macro Orientation
• Reserve enough room around Macros for IO Routing
• Reduce open fields as much as possible
• Provide necessary Blockages around the Macro.

Issues arises due to bad Floorplan

• Congestion near Macro Pins/ Corners due to insufficient Placement Blockage
• Std. Cell placement in narrow channels led to Congestion
• Macros of same partition which are placed far apart can cause Timing Violation 

Sanity Checks

• Sanity Checks mainly checks the quality of netlist in terms of timing.
• It also consists of checking the issues related to Library files, Timing constraints, IOs and Optimization Directives.
• Some of the Netlist sanity checks:
• Floating Pins
• Unconstrained Pins
• Undriven Input ports
• Unloaded Output Ports
• Pin direction mismatches.
• Multiple drivers etc.

Retention Registers

• These cells are special flops with multiple power supply.
• They are typically used as a shadow register to retain its value even if the block in which its residing is shut-down.
• All the paths leading to this register need to be ‘always_on’ and hence special care must be taken to synthesize/Place/route them.
• When design blocks are switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state, retention flip-flops must be used”
• The retention flop has the same structure as a standard flop.
• However, the retention flop has a balloon latch that is connected to always on Vdd.
• In Normal mode the state saving latch will not be active.
• Just before power down the value in the regular filp-flop will be transferred to the state saving register and the power to the regular register will be shut down.
• The power to the state saving latch shoud be maintatined and thus it keeps the register state.