Floorplanning

Steps in Floorplan

• Initialize with Chip & Core Aspect Ratio (AR)
• Initialize with Core Utilization
• Initialize Row Configuration & Cell Orientation
• Provide the Core to Pad/ IO spacing (Core to IO clearance)
• Pins/ Pads Placement
• Macro Placement by Fly-line Analysis
• Macro Placement requirements are also need to consider
• Blockage Management (Placement/ Routing)

Macro Placement

• Fly-line Analysis (For Connectivity information)
• Macro keep-out (For Uniform Standard Cell Region)
• Channel Calculation (Critical for Congestion and Timing)
• Avoid odd shaped area for Standard Cells
• Funnel shaped Macro Placements are preferred
• Fix the Macro locations, so that tool wont alter during Optimization
• Sufficient Spacing between Macros

Macro Placement Tips

• Place macros around chip periphery, so that core area will be clustered
• Consider connections to fixed cells when placing Macros
• In advanced Technology Nodes Macro Orientation is fixed since the Poly Orientation can’t vary, so there will be restrictions in Macro Orientation
• Reserve enough room around Macros for IO Routing
• Reduce open fields as much as possible
• Provide necessary Blockages around the Macro.

Issues arises due to bad Floorplan

• Congestion near Macro Pins/ Corners due to insufficient Placement Blockage
• Std. Cell placement in narrow channels led to Congestion
• Macros of same partition which are placed far apart can cause Timing Violation