Level Shifter

Level Shifter

• Purpose of this cell is to shift the signal Voltage (Low to High or High to Low) from one voltage domain to another.
• This is required when the chip is operating in multi-voltage domains.
• Generally Buffer type or Latch type Level Shifters are available.
• A Level shifter is placed in the railvoltage domain of the cell. Otherwise a new voltage area is required for such Level Shifter placement.

• Usually already present in the netlist.
• Secondary mesh is created alongside the primary.
• Level shifters on all inputs of overdrive/low voltage block to be placed inside the block.
• Placed close to the block input pins
• Level shifters are connected after virtual placement.

Import Design

Import Design:

As soon as we get the Input file we do the Import design. Where in which the following files are loaded to the PnR Tool

• Netlist
• Physical Libraries
• Timing Libraries
• Technology Files
• Constraints
• IO info File
• Power Specification File
• Optimization requirements
• Clock spec
• FP/DEF.

Physical Design Inputs

Physical Design Inputs

• Netlist (.v /.vhd)
• It contains Cell name and drive strength.
• Macros
• Standard cells ports
• Interconnection details
• Timing Libraries (.lib/.db)
• Logical view of the cells (std cell lib
• Library Exchange Format (LEF)
• Technology files (.tf/.tech.lef)
• Constrains
• Timing constraints like Clock Definition, Timing Exceptions (False Paths, Asynchronous paths)
• Delay Constraints like Latency, Input Delay, Input Transition, output Load and Output Transition.
• Power and Area constraints
• Design Rule constrains like Max Fanout, Max cap, max Transition
• Clock Uncertainty.
• Operating Conditions
• Power Specification Files
• Power Domains or ON/OFF regions
• PG nets
• Clock Tree Constrains
• Clock Def point.
• Insertion delay
• Skew Target
• Man Cap/Tran/Fanout
• Buffer levels
• List of Buffers/Inverters to use.
• NDR rules for Clock routing.
• Optimization requirements
• Dont use cells 
• Size only or use only cells
• IO Ports file
• Port locations
• Floorplan file

Physical Design Interview Questions

1. What are the inputs you get for Block level Physical Design?
• Netlist (.v /.vhd)
• Timing Libraries (.lib/.db)
• Library Exchange Format (LEF)
• Technology files (.tf/.tech.lef)
• Constrains (SDC)
• Power Specification File
• Clock Tree Constrains
• Optimization requirements
• IO Ports file
• Floorplan file
2. What are the different checks you do on the Input Netlist.
• Floating Pins
• Unconstrained pins
• Undriven input ports
• Unloaded output ports
• Pin direction mismatches
• Multiple Drivers
• Zero wire load Timing checks
• Issues with respect to the Library file, Timing Constraints, IOs and Optimization requirements.
3. How to do macro Placement in a block
• Analyse the fly-line for connectivity between Macros to Macros and between the Macros to IO ports.
• Group and Place the same hierarchy Macros together.
• Calculate/Estimate the Channel length required between Macros.
• Avoid odd shapes
• Place macros around the block periphery, so that core area will have common logic.
• Keep enough room around Macros for IO routing.
• Give necessary blockages around the Macros like Halo around the macros.
4. What are the issues you see if floorplan is bad.
• Congestion near Macro corners due to insufficient placement blockage.
• Standard cell placement in narrow channels led to congestion.
• Macros of same partition which are placed far apart can cause timing violation.
5. What are different optimization techniques?
• Cell Sizing: Size up or down to meet timing/area.
• Vt Swapping
• Cloning: fanout reduction
• Buffering: Buffers are added in the middle of long net paths to reduce the delay.
• Logical restructuring: Breaking complex cells to simpler cells or vice versa
• Pin swapping
6. What are the inputs for the CTS.
• CTS SDC
• Max Skew
• Max and Min Insertion Delay
• Max Transition, Capacitance, Fanout
• No of Buffer levels
• Buffer/Inverter list
• Clock Tree Routing Metal Layers
• Clock tree Root pin, Leaf Pin, Preserve pin, through pin and exclude pin
7. Why the Metal Fill is required
• If there is lot of gap between the routed metal layers (empty tracks), during the process of Etching the etching material used will fall more in this gap due to which Over Etching of existing metal occurs which may create opens. So in order to have uniform Metal Density across the chip, Dummy Metal is added in these empty tracks.
8. What is Metal Fill
• Metal Density Rule helps to avoid Over Etching or Metal Erosion.
• Fill the empty metal tracks with metal shapes to meet the metal density rules.
• There are two types of Metal Fill
1. Floating Metal Fill: Does not completely shield the aggressor nets, so SI will be there.
2. Grounded Metal Fill: Completely shield the aggressor nets, less SI
9. What are the reasons for routing congestion
• Inefficient floorplan
• Macro placement or macro channels is not proper.
• Placement blockages not given
• No Macro to Macro channel space given.
• High cell density
• High local utilization
• High number of complex cells like AOI/OAI cells which has more pin count are placed together.
• Placement of std cells near macros
• Logic optimization is not properly done.
• Pin density is more on edge of block
• Buffers added too many while optimization
• IO ports are crisscrossed, it needs to be properly aligned in order.
10. What are the different methods to reduce congestion.
• Review the floorplan/macro placements according to the block size and port placement.
• Add proper placement blockages in channels and around the macro boundaries.
• Reduce the local density using the percentage utilization/density screens.
• Cell padding is applied for high pin density cells, like AOI/OAI.
• Check and reorder scan chain if needed.
• Run the congestion driven placement with high effort.
• Check the power network is proper and on routing tract. If it is not on track, adjacent routing tracts may not be used, so it might lead to congestion

FinFETs

16nm/14nm FinFETs:

The current technology in VLSI industry is using the FinFET, it is a new type of multigate 3D transistor. FinFET is necessary at 16nm Node onwards. It offers good power and performance advantages and are insensitive to random dopant fluctuations compared to MOSFET transistor.

            FinFETs are Field Effect Transistors that get their name because the transistor gate wraps around the transistor’s elevated channel or Fin. By raising the channel above the substrate instead of creating the channel just below the surface, it is possible to wrap the gate around up to three of its sides, providing much greater electrostatic control over the carriers within it.

Fin-FET overcomes the short-channel effect

On a bulk-silicon process, control over fin depth is more difficult, although the manufacturing issues appear to be manageable

Self-heating is the main problem with Fin-FET devices

Margin (Slack)

            Input data is checked against the clock to ensure that it meets the setup and hold requirements that define the required window.

The difference between the valid and required times is called the margin. The difference between the setup time and the signals late event delay time is called the setup margin, or setup slack.

Margins may be either positive or negative. A positive margin means that the signal meets the timing requirement. A negative margin means that the signal does not meet the timing requirement. A negative margin indicates a timing violation.

Valid and Required Time

Valid time

            Valid time is the time during which a signal is stable. Timing defined at FUB inputs and Flip Flop outputs is used as valid time, and propagated on all paths origination at this node.

Required time

            The required time is the time during which a signal is required. This time is defined at FUB outputs and Flip Flop inputs

Timing Events

 

      A signal can become stable at different times for various reasons, for example the transition may be caused by different logic paths, or it may be affected by physical variations that affect circuit behavior. Such factors can cause the signal to transition at different points of time. Therefore a signal can become stable at latest time (a late event) and unstable at earliest time (an early event).

Late Event:

     

When you want to check whether a signal is sure to arrive in time to meet a timing requirement coming from a sampling element, you need to check the signal’s latest possible transition to a stable value. This is the late event. After this the signal is guaranteed to be stable, and you can be sure it will be stable at sampling time. The late event value is the maximal delay value, or max delay. Timing analysis based on max delays is called max delay analysis. Max delay analysis is also called setup analysis, because it is used to determine whether signals get "set up" (in the sense of "become ready") in time to be sampled correctly by sampling elements.

Early event:

When you want check whether a signal remains stable long enough to be sampled correctly, you need to check the earliest possible time when the signal can become unstable. This is the early event. The early event value is the minimal delay value, or min delay. Timing analysis based on min delays is called min delay analysis. Min delay analysis is also called hold analysis, because it is used to determine whether a signal "holds" its value long enough to be sampled correctly.

Timing Parameters and Concepts

Gate delay

The time between a 50% transition on the input to a 50% transition on the output.

It is also called as propagation delay ‘tp’.

•         Tpl2h – time to propagate low on input to high on output

•         Tph2l – time to propagate high on input to low on output

 

 

Slope

The time difference between the 20% and 80% transition on a signal. It is also known as trasition delay, wave delay.

·         SlopeL2H – Slope for a low to high transition

·         SlopeH2L – Slope for a high to low transition

Some tools use different definitions

·         Tool reports 0%-100%, measures 10%-90%

·         Most tools use 20%-80%

 

 

 

 

Clock

•         Reference clock (virtual clock, system clock) is an ideal periodic signal that serves as a common reference for all timing events. It has the following properties: Rise time, Fall time, Period. Multiple reference clocks with different frequencies may exist in the same design

•         Qualified clock is an actual circuit signal with constant relation to some reference clock. Clocks are the controlling signal of sampling/generating elements

What is Static Timing Analysis?

Introduction

            Timing analysis is a method of analyzing and solving timing problems to ensure that the design meets the target frequency. Critical timing information such as critical path delays and margins are extracted using the so called, Static Timing Analysis (STA) tool, where each delay elements are pre- characterized and propagated through the timing graph of the given design. Dynamic simulations for timing analysis is no more useful for quick timing closures as multi-core processors are large in size, for reasons like complexity of designs, spice convergence, menial task of probing critical paths etc., here a new technique is approached to handle STA on analog circuits. Pre-layout timing analysis is carried to fix the timing problems before the layout construction, since changing layout takes more time than changing schematics. Post layout is the final timing analysis with extracted parasitics. It is difficult to calculate setup and hold time violations by running STA on large designs like microprocessors. So it is simple by dividing design in to smaller designs called FUBs (Functional Unit Blocks), and collection of FUBs are called Unit. A FUB represents actual physical hardware units of distinct functionality. A well defined and compact interface exists between FUB and neighboring FUB.

Depending on the design methodologies used, two types of timing analysis methods are commonly used: Static timing analysis and dynamic timing analysis.

Static Timing Analysis

It is a non-simulation approach used to analyze propagation of delays. It computes the worst case path delays by accumulating precharacterized device delays along a given path. it does not require any input vectors to analyze the worst case delays. It allows you to run analyses on large circuits fast, but at the expense of accuracy. STA has produced a reasonably accurate timing result in the pre-silicon design phase and helped the designer to properly optimize their design to meet the given timing specification (e.g. operating frequency). 

Dynamic Timing Analysis

It is a Circuit simulation for obtaining a very accurate timing analysis of a path, using input waveforms and generating output waveforms. It is more accurate, but much slower than static timing analysis. Generally used for analog and small specific circuits. It is not path oriented, if dynamic approach results may not match the expected values, then to solve that we have to bedug the path causing the problem. If the design is large it is difficult to analyze the root cause.

What is Setup and Hold time of a Flip-Flop?

To guarantee correct data propagation in sequential cells, the data input signal must remain stable for a minimum length of time before the active edge of the clock. This period of time is called the setup time. Setup time is measured as the difference between the clock edge and data edge. The hold time is the minimum length of time the input data signal must remain stable after the active edge of the clock. Hold time is measured same as setup.