AOCV

• In lower nodes with increasing process, voltage, and temperature variations across the same die, arriving at a single Global derate number is difficult.
• OCV analysis results in reduced design performance, and longer timing closure cycles
• AOCV on the other hand  uses intelligent techniques for specific derating instead of a single global derate value
• AOCV provides a solution for longer timing closure, reduced design performance that caused with OCV analysis.
• In AOCV analysis variable values are used for derating timing paths
• Derate values are functions of Logic depth and/or net and cell location

Using silicon data from test-chips Advanced OCV computes the length of the diagonal of the bounding box. Based on the length calculated appropriate derate value is picked from the AOCV table. 

Floorplanning

Steps in Floorplan

• Initialize with Chip & Core Aspect Ratio (AR)
• Initialize with Core Utilization
• Initialize Row Configuration & Cell Orientation
• Provide the Core to Pad/ IO spacing (Core to IO clearance)
• Pins/ Pads Placement
• Macro Placement by Fly-line Analysis
• Macro Placement requirements are also need to consider
• Blockage Management (Placement/ Routing)

Macro Placement

• Fly-line Analysis (For Connectivity information)
• Macro keep-out (For Uniform Standard Cell Region)
• Channel Calculation (Critical for Congestion and Timing)
• Avoid odd shaped area for Standard Cells
• Funnel shaped Macro Placements are preferred
• Fix the Macro locations, so that tool wont alter during Optimization
• Sufficient Spacing between Macros

Macro Placement Tips

• Place macros around chip periphery, so that core area will be clustered
• Consider connections to fixed cells when placing Macros
• In advanced Technology Nodes Macro Orientation is fixed since the Poly Orientation can’t vary, so there will be restrictions in Macro Orientation
• Reserve enough room around Macros for IO Routing
• Reduce open fields as much as possible
• Provide necessary Blockages around the Macro.

Issues arises due to bad Floorplan

• Congestion near Macro Pins/ Corners due to insufficient Placement Blockage
• Std. Cell placement in narrow channels led to Congestion
• Macros of same partition which are placed far apart can cause Timing Violation 

Sanity Checks

• Sanity Checks mainly checks the quality of netlist in terms of timing.
• It also consists of checking the issues related to Library files, Timing constraints, IOs and Optimization Directives.
• Some of the Netlist sanity checks:
• Floating Pins
• Unconstrained Pins
• Undriven Input ports
• Unloaded Output Ports
• Pin direction mismatches.
• Multiple drivers etc.

Retention Registers

• These cells are special flops with multiple power supply.
• They are typically used as a shadow register to retain its value even if the block in which its residing is shut-down.
• All the paths leading to this register need to be ‘always_on’ and hence special care must be taken to synthesize/Place/route them.
• When design blocks are switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state, retention flip-flops must be used”
• The retention flop has the same structure as a standard flop.
• However, the retention flop has a balloon latch that is connected to always on Vdd.
• In Normal mode the state saving latch will not be active.
• Just before power down the value in the regular filp-flop will be transferred to the state saving register and the power to the regular register will be shut down.
• The power to the state saving latch shoud be maintatined and thus it keeps the register state.

Level Shifter

Level Shifter

• Purpose of this cell is to shift the signal Voltage (Low to High or High to Low) from one voltage domain to another.
• This is required when the chip is operating in multi-voltage domains.
• Generally Buffer type or Latch type Level Shifters are available.
• A Level shifter is placed in the railvoltage domain of the cell. Otherwise a new voltage area is required for such Level Shifter placement.

• Usually already present in the netlist.
• Secondary mesh is created alongside the primary.
• Level shifters on all inputs of overdrive/low voltage block to be placed inside the block.
• Placed close to the block input pins
• Level shifters are connected after virtual placement.

Import Design

Import Design:

As soon as we get the Input file we do the Import design. Where in which the following files are loaded to the PnR Tool

• Netlist
• Physical Libraries
• Timing Libraries
• Technology Files
• Constraints
• IO info File
• Power Specification File
• Optimization requirements
• Clock spec
• FP/DEF.

Physical Design Inputs

Physical Design Inputs

• Netlist (.v /.vhd)
• It contains Cell name and drive strength.
• Macros
• Standard cells ports
• Interconnection details
• Timing Libraries (.lib/.db)
• Logical view of the cells (std cell lib
• Library Exchange Format (LEF)
• Technology files (.tf/.tech.lef)
• Constrains
• Timing constraints like Clock Definition, Timing Exceptions (False Paths, Asynchronous paths)
• Delay Constraints like Latency, Input Delay, Input Transition, output Load and Output Transition.
• Power and Area constraints
• Design Rule constrains like Max Fanout, Max cap, max Transition
• Clock Uncertainty.
• Operating Conditions
• Power Specification Files
• Power Domains or ON/OFF regions
• PG nets
• Clock Tree Constrains
• Clock Def point.
• Insertion delay
• Skew Target
• Man Cap/Tran/Fanout
• Buffer levels
• List of Buffers/Inverters to use.
• NDR rules for Clock routing.
• Optimization requirements
• Dont use cells 
• Size only or use only cells
• IO Ports file
• Port locations
• Floorplan file

Physical Design Interview Questions

1. What are the inputs you get for Block level Physical Design?
• Netlist (.v /.vhd)
• Timing Libraries (.lib/.db)
• Library Exchange Format (LEF)
• Technology files (.tf/.tech.lef)
• Constrains (SDC)
• Power Specification File
• Clock Tree Constrains
• Optimization requirements
• IO Ports file
• Floorplan file
2. What are the different checks you do on the Input Netlist.
• Floating Pins
• Unconstrained pins
• Undriven input ports
• Unloaded output ports
• Pin direction mismatches
• Multiple Drivers
• Zero wire load Timing checks
• Issues with respect to the Library file, Timing Constraints, IOs and Optimization requirements.
3. How to do macro Placement in a block
• Analyse the fly-line for connectivity between Macros to Macros and between the Macros to IO ports.
• Group and Place the same hierarchy Macros together.
• Calculate/Estimate the Channel length required between Macros.
• Avoid odd shapes
• Place macros around the block periphery, so that core area will have common logic.
• Keep enough room around Macros for IO routing.
• Give necessary blockages around the Macros like Halo around the macros.
4. What are the issues you see if floorplan is bad.
• Congestion near Macro corners due to insufficient placement blockage.
• Standard cell placement in narrow channels led to congestion.
• Macros of same partition which are placed far apart can cause timing violation.
5. What are different optimization techniques?
• Cell Sizing: Size up or down to meet timing/area.
• Vt Swapping
• Cloning: fanout reduction
• Buffering: Buffers are added in the middle of long net paths to reduce the delay.
• Logical restructuring: Breaking complex cells to simpler cells or vice versa
• Pin swapping
6. What are the inputs for the CTS.
• CTS SDC
• Max Skew
• Max and Min Insertion Delay
• Max Transition, Capacitance, Fanout
• No of Buffer levels
• Buffer/Inverter list
• Clock Tree Routing Metal Layers
• Clock tree Root pin, Leaf Pin, Preserve pin, through pin and exclude pin
7. Why the Metal Fill is required
• If there is lot of gap between the routed metal layers (empty tracks), during the process of Etching the etching material used will fall more in this gap due to which Over Etching of existing metal occurs which may create opens. So in order to have uniform Metal Density across the chip, Dummy Metal is added in these empty tracks.
8. What is Metal Fill
• Metal Density Rule helps to avoid Over Etching or Metal Erosion.
• Fill the empty metal tracks with metal shapes to meet the metal density rules.
• There are two types of Metal Fill
1. Floating Metal Fill: Does not completely shield the aggressor nets, so SI will be there.
2. Grounded Metal Fill: Completely shield the aggressor nets, less SI
9. What are the reasons for routing congestion
• Inefficient floorplan
• Macro placement or macro channels is not proper.
• Placement blockages not given
• No Macro to Macro channel space given.
• High cell density
• High local utilization
• High number of complex cells like AOI/OAI cells which has more pin count are placed together.
• Placement of std cells near macros
• Logic optimization is not properly done.
• Pin density is more on edge of block
• Buffers added too many while optimization
• IO ports are crisscrossed, it needs to be properly aligned in order.
10. What are the different methods to reduce congestion.
• Review the floorplan/macro placements according to the block size and port placement.
• Add proper placement blockages in channels and around the macro boundaries.
• Reduce the local density using the percentage utilization/density screens.
• Cell padding is applied for high pin density cells, like AOI/OAI.
• Check and reorder scan chain if needed.
• Run the congestion driven placement with high effort.
• Check the power network is proper and on routing tract. If it is not on track, adjacent routing tracts may not be used, so it might lead to congestion

FinFETs

16nm/14nm FinFETs:

The current technology in VLSI industry is using the FinFET, it is a new type of multigate 3D transistor. FinFET is necessary at 16nm Node onwards. It offers good power and performance advantages and are insensitive to random dopant fluctuations compared to MOSFET transistor.

            FinFETs are Field Effect Transistors that get their name because the transistor gate wraps around the transistor’s elevated channel or Fin. By raising the channel above the substrate instead of creating the channel just below the surface, it is possible to wrap the gate around up to three of its sides, providing much greater electrostatic control over the carriers within it.

Fin-FET overcomes the short-channel effect

On a bulk-silicon process, control over fin depth is more difficult, although the manufacturing issues appear to be manageable

Self-heating is the main problem with Fin-FET devices