Clock Gating:

• The Clock contributes significant component of the total Power.
• A Flop will dissipate power when ever the clock toggles even if the output does not change.
• Clock gating technique minimizes the clock switching activity at the flop when the flop input is not active.
• In the given example Fig a, the flop receives new data only when the enable signal EN is active otherwise it remains the previous state.When EN is inactive, the clock toggling at the flop do not cause any output change though the clock activity still results in the power dissipated inside the flop.
• The logic restructuring through clock gating introduces gating of the clock at the flop pin. Thus it ensures that the clock pin toggles only when new data is available at its data input.

Common Path Pessimism Removal (CPPR):

• Common Path Pessimism (CPP)
• Applying different derating for the Launch and Capture Clock is overly pessimistic
• The Clock Tree will be at only one PVT condition, either as a maximum path or as a minimum path (or anything in between) but never both at the same time
• CPP is the delay difference along the common portion of the Clock Tree due to different deratings for Launch and Capture Clock Paths
• Pessimism caused by different derating factors applied on the common part of the Clock Tree is called Common Path Pessimism (CPP)/ Clock Re-convergence Pessimism (CRP) which should be removed during the analysis
• CRP or CPP = (maximum clock delay or skew) - (minimum clock delay or skew)
• Common Path Pessimism Removal (CPPR) or Clock Re-convergence Pessimism Removal (CRPR)
• Both CPPR and CRPR are removal of artificially introduced pessimism between the Launch Clock Path and the Capture Clock Path in timing analysis
• CPPR - terminology by Cadence
• CRPR - terminology by Synopsys 

Timing Path Groups:

• Timing paths are grouped into path groups by the clocks controlling their endpoints
• Input pin/port to Register
• Delays off-chip + Combinational logic delays up to the first sequential device
• Register to Register
• Start at a sequential device
• CLK-to-Q transition delay + the combinational logic delay + external delay requirements
• Register to Output pin/port
• Delay and timing constraint (Setup and Hold) times between sequential devices for synchronous clocks + source and destination clock propagation times
• Input pin/port to Output pin/port
• Delays off-chip + combinational logic delays + external delay requirements 

Multi-VT Cells:

• By implanting dopants in different concentration Different threshold voltages are achieved.
• Need Multi-VT Library
• Sub-threshold leakage varies exponentially with VT compared to the weaker dependency of delay over VT
• If the optimization target is power performance, first use the HVT cells library and then try LVT cells 
• If the optimization target is to meet timing then first use LVT cells and then HVT cells
• If you swap the capture flop from SVT to LVT or HVT, there will be very minimal setup/hold impact in most flops, it is of zero impact for hold
• If you swap the launch flop from SVT to LVT or HVT, Setup will be improve and hold will be impacted correspondingly
• High Voltage Threshold (HVT )
• Use in non-timing critical paths
• Use in power critical paths
• Has low leakage and low speed
• Low Voltage Threshold (LVT )
• Use in timing critical paths
• Use in non-power critical paths
• Has high leakage and high speed
• Standard Voltage Threshold/ Regular Voltage Threshold (SVT/ RVT)
• Medium delay and medium power requirement 

Clock Domain Crossing (CDC):

• In a Typical Design there may be more than one clock domain.
• If a path has launch and capture clocks are of different clock domains, then these are said to be Clock Domain crossing paths. 
• These CDC paths may violate the setup and Hold window, resulting in metastability. So there should be some synchronizer logic between the two clock domains.

False Path:

• In the actual functional operation of the design, it is possible that certain timing paths are not real or Practically the data never goes through that path, such paths are called False paths.
• STA does the timing analysis on all the True timing paths, all the false paths are excluded from timing analysis.
• Some examples of False paths are:
• One Clock domain to another clock domain.
• From one Clock pin of a Flip-flop to the input of another Flip-flop.
• It could be through any Pin of the cell or multiple cells or a combination of these.
• A false path is set using the set_false_path specification.
• Eg:    set_false_path –from [get_clocks SCAN_ACLK] –to [get_clocks SCAN_BCLK]
• Any path starting from SCAN_ACLK domain to SCAN_BCLK domain is a false path.

Half Cycle Path:

• Timing path that is designed to take half clock cycle (both of the clock edges) for the data to propagate from the start point to the end point.
• Both the Startpoint and Endpoint Flops should be clocked by the same Clock.
• No Need to specify the launch edge and capture edge in SDC, since the tool can identify it from the netlist.

Multi-Cycle Path:

• Timing path that is designed to take more than one clock cycle for the data to propagate from start point to the end point.
• Both the Startpoint and Endpoint Flops should be clocked by the same Clock.
• Need to specify the launch edge and capture edge in SDC

Single Cycle Path:

• With in one clock cycle the timing path that is designed for the data has to propagate from Startpoing to Endpoint.
• Both the Startpoint and Endpoint Flops should be clocked by the same Clock.
• Generally Tools will consider all the timing paths as single cycle paths.