False Path:

• In the actual functional operation of the design, it is possible that certain timing paths are not real or Practically the data never goes through that path, such paths are called False paths.
• STA does the timing analysis on all the True timing paths, all the false paths are excluded from timing analysis.
• Some examples of False paths are:
• One Clock domain to another clock domain.
• From one Clock pin of a Flip-flop to the input of another Flip-flop.
• It could be through any Pin of the cell or multiple cells or a combination of these.
• A false path is set using the set_false_path specification.
• Eg:    set_false_path –from [get_clocks SCAN_ACLK] –to [get_clocks SCAN_BCLK]
• Any path starting from SCAN_ACLK domain to SCAN_BCLK domain is a false path.