Clock Gating:

• The Clock contributes significant component of the total Power.
• A Flop will dissipate power when ever the clock toggles even if the output does not change.
• Clock gating technique minimizes the clock switching activity at the flop when the flop input is not active.
• In the given example Fig a, the flop receives new data only when the enable signal EN is active otherwise it remains the previous state.When EN is inactive, the clock toggling at the flop do not cause any output change though the clock activity still results in the power dissipated inside the flop.
• The logic restructuring through clock gating introduces gating of the clock at the flop pin. Thus it ensures that the clock pin toggles only when new data is available at its data input.