Timing Path Groups:

• Timing paths are grouped into path groups by the clocks controlling their endpoints
• Input pin/port to Register
• Delays off-chip + Combinational logic delays up to the first sequential device
• Register to Register
• Start at a sequential device
• CLK-to-Q transition delay + the combinational logic delay + external delay requirements
• Register to Output pin/port
• Delay and timing constraint (Setup and Hold) times between sequential devices for synchronous clocks + source and destination clock propagation times
• Input pin/port to Output pin/port
• Delays off-chip + combinational logic delays + external delay requirements