Temperature Inversion

In Current equation, I = K.μ.( VGS - VTH)2 ; where mobility (μ) and Threshold Voltage (VTH) are functions of Temperature

At high voltage μ determines the Drain current where as at lower voltages VTH determines the drain current. So at higher voltages device delay increase with temperature but at lower voltages, device delay decreases with temperature

At advanced Technology Nodes though the Threshold Voltage has not reduced much, but the Gate Overdrive Voltage has reduced due to the reduction of supply voltages

Temperature Inversion Effects are more observed in Technology Nodes below 40nm

Multiple Patterning

• Involves decomposing the design across multiple masks to allow the printing of tighter pitches

• 38-nm features with 193-nm light water immersion lithography is the limitation with the current lithographic process

• Multiple Patterning is a technique used in the lithographic process that can create the features less than 38nm at advanced process nodes

• Multiple patterning basically changing the value of K1 in the Critical Dimension equation

Double Patterning

• Double patterning counters the effects of diffraction in optical lithography
• Diffraction effects makes it difficult to produce accurately defined deep sub-micron patterns using existing lighting sources and conventional masks
• Diffraction effects makes sharp corners and edges become blur, and some small features on the mask won’t appear on the wafer at all
• Double patterning is expensive because it uses two masks to define a layer that was defined with one at previous process nodes

Design for Manufacturability (DFM)

• Techniques to ensure the design can manufacture successfully with high yield
• To ensures survival of the design, during the complex fabrication process
• Lithography, etch, Chemical Mechanical Polishing (CMP), and mask systematic manufacturing variations surpass random variations as the prime limiters to catastrophic and parametric yield loss

Need for DFM

• Current Lithographic techniques (193nm Laser) cannot print deep-submicron technology patterns without distortion
• Higher design complexity and shrinking device geometries
• More devices per unit area on a chip (device density)

Importance of DFM

• Impact of variations, if not addressed in the design, will cause manufacturing issues, such as poor yields, long yield ramp-up times and poor reliability
• The chips may completely miss the market window or may hit the market window but not economically viable
• The chips may still function, but not at the required/expected speed
• The chips appear to be reliable after volume production, but may suffer catastrophic failures in the field earlier than their expected life-cycle

Clock Gating:

• The Clock contributes significant component of the total Power.
• A Flop will dissipate power when ever the clock toggles even if the output does not change.
• Clock gating technique minimizes the clock switching activity at the flop when the flop input is not active.
• In the given example Fig a, the flop receives new data only when the enable signal EN is active otherwise it remains the previous state.When EN is inactive, the clock toggling at the flop do not cause any output change though the clock activity still results in the power dissipated inside the flop.
• The logic restructuring through clock gating introduces gating of the clock at the flop pin. Thus it ensures that the clock pin toggles only when new data is available at its data input.

Common Path Pessimism Removal (CPPR):

• Common Path Pessimism (CPP)
• Applying different derating for the Launch and Capture Clock is overly pessimistic
• The Clock Tree will be at only one PVT condition, either as a maximum path or as a minimum path (or anything in between) but never both at the same time
• CPP is the delay difference along the common portion of the Clock Tree due to different deratings for Launch and Capture Clock Paths
• Pessimism caused by different derating factors applied on the common part of the Clock Tree is called Common Path Pessimism (CPP)/ Clock Re-convergence Pessimism (CRP) which should be removed during the analysis
• CRP or CPP = (maximum clock delay or skew) - (minimum clock delay or skew)
• Common Path Pessimism Removal (CPPR) or Clock Re-convergence Pessimism Removal (CRPR)
• Both CPPR and CRPR are removal of artificially introduced pessimism between the Launch Clock Path and the Capture Clock Path in timing analysis
• CPPR - terminology by Cadence
• CRPR - terminology by Synopsys 

Timing Path Groups:

• Timing paths are grouped into path groups by the clocks controlling their endpoints
• Input pin/port to Register
• Delays off-chip + Combinational logic delays up to the first sequential device
• Register to Register
• Start at a sequential device
• CLK-to-Q transition delay + the combinational logic delay + external delay requirements
• Register to Output pin/port
• Delay and timing constraint (Setup and Hold) times between sequential devices for synchronous clocks + source and destination clock propagation times
• Input pin/port to Output pin/port
• Delays off-chip + combinational logic delays + external delay requirements 

Multi-VT Cells:

• By implanting dopants in different concentration Different threshold voltages are achieved.
• Need Multi-VT Library
• Sub-threshold leakage varies exponentially with VT compared to the weaker dependency of delay over VT
• If the optimization target is power performance, first use the HVT cells library and then try LVT cells 
• If the optimization target is to meet timing then first use LVT cells and then HVT cells
• If you swap the capture flop from SVT to LVT or HVT, there will be very minimal setup/hold impact in most flops, it is of zero impact for hold
• If you swap the launch flop from SVT to LVT or HVT, Setup will be improve and hold will be impacted correspondingly
• High Voltage Threshold (HVT )
• Use in non-timing critical paths
• Use in power critical paths
• Has low leakage and low speed
• Low Voltage Threshold (LVT )
• Use in timing critical paths
• Use in non-power critical paths
• Has high leakage and high speed
• Standard Voltage Threshold/ Regular Voltage Threshold (SVT/ RVT)
• Medium delay and medium power requirement 

Clock Domain Crossing (CDC):

• In a Typical Design there may be more than one clock domain.
• If a path has launch and capture clocks are of different clock domains, then these are said to be Clock Domain crossing paths. 
• These CDC paths may violate the setup and Hold window, resulting in metastability. So there should be some synchronizer logic between the two clock domains.

False Path:

• In the actual functional operation of the design, it is possible that certain timing paths are not real or Practically the data never goes through that path, such paths are called False paths.
• STA does the timing analysis on all the True timing paths, all the false paths are excluded from timing analysis.
• Some examples of False paths are:
• One Clock domain to another clock domain.
• From one Clock pin of a Flip-flop to the input of another Flip-flop.
• It could be through any Pin of the cell or multiple cells or a combination of these.
• A false path is set using the set_false_path specification.
• Eg:    set_false_path –from [get_clocks SCAN_ACLK] –to [get_clocks SCAN_BCLK]
• Any path starting from SCAN_ACLK domain to SCAN_BCLK domain is a false path.

Half Cycle Path:

• Timing path that is designed to take half clock cycle (both of the clock edges) for the data to propagate from the start point to the end point.
• Both the Startpoint and Endpoint Flops should be clocked by the same Clock.
• No Need to specify the launch edge and capture edge in SDC, since the tool can identify it from the netlist.

Multi-Cycle Path:

• Timing path that is designed to take more than one clock cycle for the data to propagate from start point to the end point.
• Both the Startpoint and Endpoint Flops should be clocked by the same Clock.
• Need to specify the launch edge and capture edge in SDC

Single Cycle Path:

• With in one clock cycle the timing path that is designed for the data has to propagate from Startpoing to Endpoint.
• Both the Startpoint and Endpoint Flops should be clocked by the same Clock.
• Generally Tools will consider all the timing paths as single cycle paths.

AOCV

• In lower nodes with increasing process, voltage, and temperature variations across the same die, arriving at a single Global derate number is difficult.
• OCV analysis results in reduced design performance, and longer timing closure cycles
• AOCV on the other hand  uses intelligent techniques for specific derating instead of a single global derate value
• AOCV provides a solution for longer timing closure, reduced design performance that caused with OCV analysis.
• In AOCV analysis variable values are used for derating timing paths
• Derate values are functions of Logic depth and/or net and cell location

Using silicon data from test-chips Advanced OCV computes the length of the diagonal of the bounding box. Based on the length calculated appropriate derate value is picked from the AOCV table. 

Floorplanning

Steps in Floorplan

• Initialize with Chip & Core Aspect Ratio (AR)
• Initialize with Core Utilization
• Initialize Row Configuration & Cell Orientation
• Provide the Core to Pad/ IO spacing (Core to IO clearance)
• Pins/ Pads Placement
• Macro Placement by Fly-line Analysis
• Macro Placement requirements are also need to consider
• Blockage Management (Placement/ Routing)

Macro Placement

• Fly-line Analysis (For Connectivity information)
• Macro keep-out (For Uniform Standard Cell Region)
• Channel Calculation (Critical for Congestion and Timing)
• Avoid odd shaped area for Standard Cells
• Funnel shaped Macro Placements are preferred
• Fix the Macro locations, so that tool wont alter during Optimization
• Sufficient Spacing between Macros

Macro Placement Tips

• Place macros around chip periphery, so that core area will be clustered
• Consider connections to fixed cells when placing Macros
• In advanced Technology Nodes Macro Orientation is fixed since the Poly Orientation can’t vary, so there will be restrictions in Macro Orientation
• Reserve enough room around Macros for IO Routing
• Reduce open fields as much as possible
• Provide necessary Blockages around the Macro.

Issues arises due to bad Floorplan

• Congestion near Macro Pins/ Corners due to insufficient Placement Blockage
• Std. Cell placement in narrow channels led to Congestion
• Macros of same partition which are placed far apart can cause Timing Violation 

Sanity Checks

• Sanity Checks mainly checks the quality of netlist in terms of timing.
• It also consists of checking the issues related to Library files, Timing constraints, IOs and Optimization Directives.
• Some of the Netlist sanity checks:
• Floating Pins
• Unconstrained Pins
• Undriven Input ports
• Unloaded Output Ports
• Pin direction mismatches.
• Multiple drivers etc.

Retention Registers

• These cells are special flops with multiple power supply.
• They are typically used as a shadow register to retain its value even if the block in which its residing is shut-down.
• All the paths leading to this register need to be ‘always_on’ and hence special care must be taken to synthesize/Place/route them.
• When design blocks are switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state, retention flip-flops must be used”
• The retention flop has the same structure as a standard flop.
• However, the retention flop has a balloon latch that is connected to always on Vdd.
• In Normal mode the state saving latch will not be active.
• Just before power down the value in the regular filp-flop will be transferred to the state saving register and the power to the regular register will be shut down.
• The power to the state saving latch shoud be maintatined and thus it keeps the register state.

Level Shifter

Level Shifter

• Purpose of this cell is to shift the signal Voltage (Low to High or High to Low) from one voltage domain to another.
• This is required when the chip is operating in multi-voltage domains.
• Generally Buffer type or Latch type Level Shifters are available.
• A Level shifter is placed in the railvoltage domain of the cell. Otherwise a new voltage area is required for such Level Shifter placement.

• Usually already present in the netlist.
• Secondary mesh is created alongside the primary.
• Level shifters on all inputs of overdrive/low voltage block to be placed inside the block.
• Placed close to the block input pins
• Level shifters are connected after virtual placement.

Import Design

Import Design:

As soon as we get the Input file we do the Import design. Where in which the following files are loaded to the PnR Tool

• Netlist
• Physical Libraries
• Timing Libraries
• Technology Files
• Constraints
• IO info File
• Power Specification File
• Optimization requirements
• Clock spec
• FP/DEF.

Physical Design Inputs

Physical Design Inputs

• Netlist (.v /.vhd)
• It contains Cell name and drive strength.
• Macros
• Standard cells ports
• Interconnection details
• Timing Libraries (.lib/.db)
• Logical view of the cells (std cell lib
• Library Exchange Format (LEF)
• Technology files (.tf/.tech.lef)
• Constrains
• Timing constraints like Clock Definition, Timing Exceptions (False Paths, Asynchronous paths)
• Delay Constraints like Latency, Input Delay, Input Transition, output Load and Output Transition.
• Power and Area constraints
• Design Rule constrains like Max Fanout, Max cap, max Transition
• Clock Uncertainty.
• Operating Conditions
• Power Specification Files
• Power Domains or ON/OFF regions
• PG nets
• Clock Tree Constrains
• Clock Def point.
• Insertion delay
• Skew Target
• Man Cap/Tran/Fanout
• Buffer levels
• List of Buffers/Inverters to use.
• NDR rules for Clock routing.
• Optimization requirements
• Dont use cells 
• Size only or use only cells
• IO Ports file
• Port locations
• Floorplan file

Physical Design Interview Questions

1. What are the inputs you get for Block level Physical Design?
• Netlist (.v /.vhd)
• Timing Libraries (.lib/.db)
• Library Exchange Format (LEF)
• Technology files (.tf/.tech.lef)
• Constrains (SDC)
• Power Specification File
• Clock Tree Constrains
• Optimization requirements
• IO Ports file
• Floorplan file
2. What are the different checks you do on the Input Netlist.
• Floating Pins
• Unconstrained pins
• Undriven input ports
• Unloaded output ports
• Pin direction mismatches
• Multiple Drivers
• Zero wire load Timing checks
• Issues with respect to the Library file, Timing Constraints, IOs and Optimization requirements.
3. How to do macro Placement in a block
• Analyse the fly-line for connectivity between Macros to Macros and between the Macros to IO ports.
• Group and Place the same hierarchy Macros together.
• Calculate/Estimate the Channel length required between Macros.
• Avoid odd shapes
• Place macros around the block periphery, so that core area will have common logic.
• Keep enough room around Macros for IO routing.
• Give necessary blockages around the Macros like Halo around the macros.
4. What are the issues you see if floorplan is bad.
• Congestion near Macro corners due to insufficient placement blockage.
• Standard cell placement in narrow channels led to congestion.
• Macros of same partition which are placed far apart can cause timing violation.
5. What are different optimization techniques?
• Cell Sizing: Size up or down to meet timing/area.
• Vt Swapping
• Cloning: fanout reduction
• Buffering: Buffers are added in the middle of long net paths to reduce the delay.
• Logical restructuring: Breaking complex cells to simpler cells or vice versa
• Pin swapping
6. What are the inputs for the CTS.
• CTS SDC
• Max Skew
• Max and Min Insertion Delay
• Max Transition, Capacitance, Fanout
• No of Buffer levels
• Buffer/Inverter list
• Clock Tree Routing Metal Layers
• Clock tree Root pin, Leaf Pin, Preserve pin, through pin and exclude pin
7. Why the Metal Fill is required
• If there is lot of gap between the routed metal layers (empty tracks), during the process of Etching the etching material used will fall more in this gap due to which Over Etching of existing metal occurs which may create opens. So in order to have uniform Metal Density across the chip, Dummy Metal is added in these empty tracks.
8. What is Metal Fill
• Metal Density Rule helps to avoid Over Etching or Metal Erosion.
• Fill the empty metal tracks with metal shapes to meet the metal density rules.
• There are two types of Metal Fill
1. Floating Metal Fill: Does not completely shield the aggressor nets, so SI will be there.
2. Grounded Metal Fill: Completely shield the aggressor nets, less SI
9. What are the reasons for routing congestion
• Inefficient floorplan
• Macro placement or macro channels is not proper.
• Placement blockages not given
• No Macro to Macro channel space given.
• High cell density
• High local utilization
• High number of complex cells like AOI/OAI cells which has more pin count are placed together.
• Placement of std cells near macros
• Logic optimization is not properly done.
• Pin density is more on edge of block
• Buffers added too many while optimization
• IO ports are crisscrossed, it needs to be properly aligned in order.
10. What are the different methods to reduce congestion.
• Review the floorplan/macro placements according to the block size and port placement.
• Add proper placement blockages in channels and around the macro boundaries.
• Reduce the local density using the percentage utilization/density screens.
• Cell padding is applied for high pin density cells, like AOI/OAI.
• Check and reorder scan chain if needed.
• Run the congestion driven placement with high effort.
• Check the power network is proper and on routing tract. If it is not on track, adjacent routing tracts may not be used, so it might lead to congestion